HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 341

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

8. Initial Output in Complementary PWM Mode:
Negative phase
Positive phase
In complementary PWM mode, the initial output is determined by the setting of bits OLSN and
OLSP in the timer output control register (TOCR).
This initial output is the PWM pulse non-active level, and is output from when complementary
PWM mode is set with the timer mode register (TMDR) until TCNT_4 exceeds the value set in
the dead time register (TDDR). Figure 11.38 shows an example of the initial output in
complementary PWM mode.
An example of the waveform when the initial PWM duty value is smaller than the TDDR
value is shown in figure 11.39.
Figure 11.38
output
output
Timer output control register settings
OLSN bit: 0 (initial output: high; active level: low)
OLSP bit: 0 (initial output: high; active level: low)
Complementary
PWM mode
(TMDR setting)
Example of Initial Output in Complementary PWM Mode (1)
Initial output
TGR4_A
TCNT3, 4 value
TDDR
TCNT3, 4 count start
(TSTR setting)
Active level
11.
Rev.4.00 Mar. 27, 2008 Page 297 of 882
Dead time
Multi-Function Timer Pulse Unit (MTU)
TCNT_3
TCNT_4
Active level
REJ09B0108-0400
Time