HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 553

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(Slave data output)
14.4.5
In the slave receive mode of the I
data, and the slave device returns acknowledgements of reception. The slave device compares the
address of the slave address and the slave address of the first frame issued after the start condition
issuance by the master device. If the addresses match, the slave device operates as a slave device
specified by the master device.
Reception with HNDS Function (HNDS = 1):
Figure 14.17 is a flowchart that gives an example of operations in slave receive mode (HNDS =
1).
(Master output)
Figure 14.16 An Example of the Stop Condition Issuance Timing in Master Receive Mode
(Master output)
User processing
SCL
SDA
ICDR
SDA
IRTR
IRIC
Data 2
Operations in Slave Reception
bit 0
8
[
[6] IRIC clear
[3]
4
]
[8] Wait time for one cycle
Data 1
IRTR=0
A
[7] Set ACKB to 1
[
4
9
]
[3]
IRTR=1
[9] Set TRS to 1
bit 7
1
(MLS = ACKB = 0, WAIT = 1)
2
C bus format, the master device transmits the transmit clock and
bit 6
2
[11] IRIC clear
[10] ICDR read
bit 5
(data 2)
3
Data 3
Data 2
bit 4
4
bit 3
5
bit 2
6
Rev.4.00 Mar. 27, 2008 Page 509 of 882
bit 1
[14] IRIC clear
7
bit 0
8
14. I
[12]
[
13
]
[15] Clear WAIT to 0,
IRTR=0
2
A
C Bus Interface (IIC) Option
IRIC clear
[16] ICDR read (data 3)
[
[12]
13
9
]
IRTR=1
REJ09B0108-0400
Data 3
Stop condition generation
[17] Stop condition
issuance