HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 437

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

This LSI has four independent serial communication interface (SCI) channels. The SCI can handle
both asynchronous and clocked synchronous serial communication. Serial data communication
can be carried out with standard asynchronous communication chips such as a Universal
Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter
(ACIA). A function is also provided for serial communication between processors (multiprocessor
communication function). The SCI also supports a smart card (IC card) interface conforming to
ISO/IEC 7816-3 (Identification Card) as an extension function for asynchronous mode.
13.1
• Choice of asynchronous or clocked synchronous serial communication mode
• Full-duplex communication capability
• On-chip baud rate generator allows any bit rate to be selected
• Choice of LSB-first or MSB-first transfer* (except in the case of asynchronous mode 7-bit
• Four interrupt sources
• Module standby mode can be set
Asynchronous mode
• Data length: 7 or 8 bits
• Stop bit length: 1 or 2 bits
• Parity: Even, odd, or none
• Communication between multiprocessors
• Receive error detection: Parity, overrun, and framing errors
• Break detection: Break can be detected by reading the RxD pin level directly in case of a
SCIS200B_030020030800
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously.
Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data.
External clock can be selected as a transfer clock source (except for a smart card interface).
data)
Four interrupt sources — transmit-end, transmit-data-empty, receive-data-full, and receive
error — that can issue requests.
The transmit-data-empty interrupt and receive data full interrupts can activate the direct
memory access controller (DMAC) and the data transfer controller (DTC).
framing error
Section 13 Serial Communication Interface (SCI)
Features
13. Serial Communication Interface (SCI)
Rev.4.00 Mar. 27, 2008 Page 393 of 882
REJ09B0108-0400