HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 428

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12. Watchdog Timer
12.3.3
RSTCSR is an 8-bit readable/writable register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal.
Note:
Rev.4.00 Mar. 27, 2008 Page 384 of 882
REJ09B0108-0400
Bit
7
6
5
4 to 0 —
Bit Name
WOVF
RSTE
RSTS
*
Reset Control/Status Register (RSTCSR)
Only 0 can be written for flag clearing.
0
0
All 1
Initial Value
0
R/W
R/(W)*
R/W
R/W
R
Description
Watchdog Timer Overflow Flag
This bit is set when TCNT overflows in watchdog
timer mode. This bit cannot be set in interval timer
mode.
[Setting condition]
•
[Clearing condition]
•
Reset Enable
Specifies whether or not an internal reset signal is
generated in the chip if TCNT overflows in watchdog
timer mode.
0: Internal reset signal is not generated even if
1: Internal reset signal is generated if TCNT
Reset Select
Selects the type of internal reset generated if TCNT
overflows in watchdog timer mode.
0: Power-on reset
1: Manual reset
Reserved
These bits are always read as 1. The write value
should always be 1.
TCNT overflows
(Though this LSI is not reset, TCNT and TCSR in
WDT are reset)
overflows
Set when TCNT overflows in watchdog timer
mode
Cleared by reading WOVF, and then writing 0 to
WOVF