HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 477

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

13.4.6
Figure 13.8 shows an example of the operation for reception in asynchronous mode. In serial
reception, the SCI operates as described below.
1. The SCI monitors the communication line, and if a start bit is detected, performs internal
2. If an overrun error (when reception of the next data is completed while the RDRF flag is still
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive
5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
set to 1) occurs, the OER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an
ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag
remains to be set to 1.
RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated.
data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt
request is generated.
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt processing routine reads the receive data transferred to
RDR before reception of the next receive data has finished, continuous reception can be
enabled.
RDRF
FER
RxD
Serial Data Reception (Asynchronous Mode)
1
Start
bit
0
Figure 13.8 Example of SCI Operation in Reception
D0
(Example with 8-Bit Data, Parity, One Stop Bit)
D1
1 frame
Data
D7
Parity
bit
RXI interrupt
request
generated
0/1
Stop
bit
1
Start
bit
0
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
processing routine
D0
13. Serial Communication Interface (SCI)
Rev.4.00 Mar. 27, 2008 Page 433 of 882
D1
Data
D7
Parity
bit
0/1
ERI interrupt
request generated
by framing error
Stop
bit
1
REJ09B0108-0400
Idle state
(mark state)
1