HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 722

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

19. Flash Memory (F-ZTAT Version)
19.8.2
When erasing flash memory, the erase/erase-verify flowchart shown in figure 19.10 should be
followed.
1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Erasing is performed in block units. Make only a single-bit specification in the erase block
3. The time during which the E bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An
5. For a dummy write to a verify address, write 1-byte data H'FF to the read address. Verify data
6. If the read data is not erased successfully, set erase mode again, and repeat the erase/erase-
19.8.3
All interrupts, including the NMI interrupt, are disabled while flash memory is being programmed
or erased, or while the boot program is executing, for the following three reasons:
1. An interrupt during programming/erasing may cause a violation of the programming or erasing
2. If an interrupt exception handling starts before the vector address is written or during
3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be
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register 1 (EBR1) and the erase block register 2 (EBR2). To erase multiple blocks, each block
must be erased in turn.
overflow cycle of approximately 19.8 ms is allowed.
can be read in longwords from the address to which a dummy write was performed.
verify sequence as before. The number of repetitions of the erase/erase-verify sequence should
not exceed the maximum number of erasing (N).
algorithm, with the result that normal operation cannot be assured.
programming/erasing, a correct vector cannot be fetched and the CPU malfunctions.
carried out.
Erase/Erase-Verify Mode
Interrupt Handling when Programming/Erasing Flash Memory