HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 494

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

13. Serial Communication Interface (SCI)
Rev.4.00 Mar. 27, 2008 Page 450 of 882
REJ09B0108-0400
Figure 13.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
Note: When switching from transmit or receive operation to simultaneous transmit and receive operations,
No
No
No
first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously.
Clear TE and RE bits in SCR to 0
Write transmit data to TDR and
Read receive data in RDR, and
clear RDRF flag in SSR to 0
Start transmission/reception
clear TDRE flag in SSR to 0
Read ORER flag in SSR
Read RDRF flag in SSR
Read TDRE flag in SSR
All data received?
Initialization
ORER = 1
RDRF = 1
TDRE = 1
<End>
Yes
Yes
Yes
No
Error processing
Yes
[1]
[2]
[4]
[5]
[3]
[1] SCI initialization:
[2] SCI status check and transmit data write:
[3] Receive error processing:
[4] SCI status check and receive data read:
[5] Serial transmission/reception continuation
Set the TxD and RxD pins using the PFC.
Read SSR and check that the TDRE flag
is set to 1, then write transmit data to
TDR and clear the TDRE flag to 0.
Transition of the TDRE flag from 0 to 1
can also be identified by a TXI interrupt.
If a receive error occurs, read the ORER
flag in SSR, and after performing the
appropriate error processing, clear the
ORER flag to 0. Transmission/reception
cannot be resumed if the ORER flag is
set to 1.
Read SSR and check that the RDRF flag
is set to 1, then read the receive data in
RDR and clear the RDRF flag to 0.
Transition of the RDRF flag from 0 to 1
can also be identified by an RXI interrupt.
procedure:
To continue serial transmission/
reception, before the MSB (bit 7) of the
current frame is received, finish reading
the RDRF flag, reading RDR, and
clearing the RDRF flag to 0. Also, before
the MSB (bit 7) of the current frame is
transmitted, read 1 from the TDRE flag to
confirm that writing is possible. Then
write data to TDR and clear the TDRE
flag to 0.
Checking and clearing of the TDRE flag is
automatic when the DMAC or DTC is
activated by a transmit data empty
interrupt (TXI) request and data is written
to TDR. Also, the RDRF flag is cleared
automatically when the DMAC or DTC is
activated by a receive data full interrupt
(RXI) request and the RDR value is read.