HD6417144 RENESAS [Renesas Technology Corp], HD6417144 Datasheet - Page 426

• Manufacturer Part Number: HD6417144
• Description: 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12. Watchdog Timer
12.3.2
TCSR is an 8-bit readable/writable register. Its functions include selecting the clock source to be
input to TCNT, and the timer mode.
Rev.4.00 Mar. 27, 2008 Page 382 of 882
REJ09B0108-0400
Bit
7
6
5
Bit Name
OVF
WT/IT
TME
Timer Control/Status Register (TCSR)
0
0
Initial Value
0
R/W
R/(W)*
R/W
R/W
1
Description
Overflow Flag
Indicates that TCNT has overflowed in interval timer
mode. Only a write of 0 is permitted, to clear the
flag. This flag is not set in watchdog timer mode.
[Setting condition]
•
[Clearing condition]
•
Timer Mode Select
Selects whether the WDT is used as a watchdog
timer or interval timer. When TCNT overflows, the
WDT either generates an interval timer interrupt
(ITI) or generates a WDTOVF signal, depending on
the mode selected.
0: Interval timer mode
1: Watchdog timer mode
Timer Enable
Enables or disables the timer.
0: Timer disabled
1: Timer enabled
Interval timer interrupt (ITI) request to the CPU
when TCNT overflows
WDTOVF signal output externally when TCNT
overflows.
For details on the TCNT overflow in watchdog
timer mode, see section 12.3.3, Reset
Control/Status Register (RSTCSR).
TCNT is initialized to H'00 and count-up stops
TCNT starts counting. A WDTOVF signal or
interrupt is generated when TCNT overflows.
When TCNT overflows in interval timer mode.
When writing 0 to this bit after reading this bit or
when writing 0 to the TME bit in interval timer
mode.