Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 113

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

PS025011-1010
COMPARE Mode
In COMPARE mode, the timer counts up to the 16-bit maximum Compare value stored in
the Timer Reload High and Low Byte registers. The Timer counts timer clocks up to 
16-bit Reload value. On reaching the Compare value, the timer generates an interrupt and
counting continues (the timer value is not reset to
alternate function is enabled, the Timer Output pin changes state (from Low to High or
from High to Low) on Compare.
If the Timer reaches
Follow the steps below for configuring a timer for COMPARE mode and initiating the
count:
1. Write to the Timer Control 1 register to:
2. Write to the Timer Control 2 register to choose the timer clock source.
3. Write to the Timer Control 0 register to set the timer interrupt configuration field
4. Write to the Timer High and Low Byte registers to set the starting count value.
5. Write to the Timer Reload High and Low Byte registers to set the Compare value.
6. If desired, enable the timer interrupt and set the timer interrupt priority by writing to
7. When using the Timer Output function, configure the associated GPIO port pin for the
8. Write to the Timer Control 1 register to enable the timer and initiate counting.
In COMPARE mode, the timer clock always provides the timer input. The Compare time
is given by the following equation:
GATED Mode
In GATED mode, the timer counts only when the Timer Input signal is in its active state
(asserted) as determined by the TPOL bit in the Timer Control 1 register. When the Timer
Input signal is asserted, counting begins. A Timer Interrupt is generated when the Timer
Input signal is deasserted or a timer reload occurs. To determine if a Timer Input signal
COMPARE Mode Time (s)
–
–
–
–
TICONFIG.
the relevant interrupt registers.
Timer Output alternate function.
Disable the timer
Configure the timer for COMPARE mode
Set the prescale valu.
Set the initial logic level (High or Low) for the Timer Output alternate function, if
required
FFFFH
, the timer rolls over to
P R E L I M I N A R Y
=

-------------------------------------------------------------------------------------------------------------- -
Compare Value - Start Value
Timer Clock Frequency (Hz)
0001H
0000H
Z8 Encore! XP
). Also, if the Timer Output
 Prescale
and continue counting.

Product Specification
®
F1680 Series
Timers
99