Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 255
Z8F16800144ZCOG
Manufacturer Part Number
Z8F16800144ZCOG
Description
KIT DEV FOR Z8F642 MCU 44 PIN
Manufacturer
Zilog
Series
Z8 Encore!®r
Type
MCUr
Specifications of Z8F16800144ZCOG
Contents
Hardware, Software and Documentation
For Use With/related Products
Z8F642
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4678
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Table 126. I
BITS
FIELD
RESET
R/W
ADDR
PS025011-1010
2
C State Register (I2CSTATE)—Description when DIAG = 0
ACKV
R
7
0
ACKV—ACK Valid
This bit is set, if sending data (Master or Slave) and the
the byte just transmitted. This bit can be monitored if it is appropriate for software to
verify the
data register must not be written when
ACKV
is ended by a
ACK—Acknowledge
This bit indicates the status of the Acknowledge for the last byte transmitted or
received. This bit is set for an Acknowledge and cleared for a Not Acknowledge condi-
tion.
AS—Address State
This bit is active High while the address is being transferred on the I
DS—Data State
This bit is active high while the data is being transferred on the I
10B—This bit indicates whether a 7-bit or 10-bit address is being transmitted when
operating as a Master. After the
address are
RSTR—RESTART
This bit is updated each time a
I2CISTAT Register).
0 =
1 =
SCLOUT—Serial Clock Output
Current value of Serial Clock being output onto the bus. The actual values of the SCL and
SDA signals on the I
BUSY—I
0 = No activity on the I
1 = A transaction is underway on the I
STOP
RESTART
to assert. This bit clears when transmission of the next byte begins or the transaction
ACK
condition.
2
ACK
C Bus Busy
R
6
0
11110B
STOP
condition.
value before writing the next byte to be sent. To operate in this mode, the
or
, this bit is set. When set, it is Reset once the address has been sent.
2
C bus can be observed via the GPIO Input Register.
AS
RESTART
R
2
5
0
C Bus.
P R E L I M I N A R Y
STOP
START
condition.
DS
R
4
0
or
2
TDRE
C bus.
F55H
bit is set, if the five most-significant bits of the
RESTART
asserts; instead, the software waits for
10B
R
3
0
interrupt occurs (
Z8 Encore! XP
ACK
RSTR
R
2
0
bit in this register is valid for
Product Specification
2
I2C Master/Slave Controller
C bus.
SPRS
SCLOUT
2
C bus.
R
1
1
®
bit set in
F1680 Series
BUSY
R
0
0
241
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