Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 211
Z8F16800144ZCOG
Manufacturer Part Number
Z8F16800144ZCOG
Description
KIT DEV FOR Z8F642 MCU 44 PIN
Manufacturer
Zilog
Series
Z8 Encore!®r
Type
MCUr
Specifications of Z8F16800144ZCOG
Contents
Hardware, Software and Documentation
For Use With/related Products
Z8F642
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4678
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PS025011-1010
Input Sample Time
Slave Select Modes of Operation
(CLKPOL = 0)
(CLKPOL = 1)
This section describes the different modes of data transfer supported by the ESPI block.
The mode is selected by the Slave Select Mode (SSMD) field of the Mode Register.
SPI Mode
This mode is selected by setting the SSMD field of the Mode Register to 00. In this mode
software controls the assertion of the SS signal directly via the SSV bit of the SPI
Transmit Data Command register. Software can be used to control an SPI mode
transaction. Prior to or simultaneously with writing the first transmit data byte; software
sets the SSV bit. Software sets the SSV bit either by performing a byte write to the
Transmit Data Command register prior to writing the first transmit character to the Data
register or by performing a word write to the Data register address which loads the first
transmit character and simultaneously sets the SSV bit. SS will remain asserted when one
or more characters are transferred. There are two mechanisms for deasserting SS at the
end of the transaction. One method used by software is to set the TEOF bit of the Transmit
Data Command register, when the last TDRE interrupt is being serviced (set TEOF before
or simultaneously with writing the last data byte). Once the last bit of the last character is
MOSI
MISO
SCK
SCK
SS
Figure 35. ESPI Timing when PHASE = 1
Bit7
Bit7
Bit6
Bit6
P R E L I M I N A R Y
Bit5
Bit5
Bit4
Bit4
Bit3
Bit3
Z8 Encore! XP
Enhanced Serial Peripheral Interface
Bit2
Bit2
Product Specification
Bit1
Bit1
®
F1680 Series
Bit0
Bit0
197
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