Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 302
Z8F16800144ZCOG
Manufacturer Part Number
Z8F16800144ZCOG
Description
KIT DEV FOR Z8F642 MCU 44 PIN
Manufacturer
Zilog
Series
Z8 Encore!®r
Type
MCUr
Specifications of Z8F16800144ZCOG
Contents
Hardware, Software and Documentation
For Use With/related Products
Z8F642
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4678
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PS025011-1010
OCD Data Format
OCD Auto-Baud Detector/Generator
•
•
•
•
•
Exiting DEBUG Mode
The device exits DEBUG mode following any of these operations:
•
•
•
•
•
The On-Chip Debugger (OCD) interface uses the asynchronous data format defined for
RS-232. Each character is transmitted as 1 Start bit, 8 data bits (least-significant bit first),
and 1 Stop bit (see
To run over a range of baud rates (bits per second) with various system clock frequencies,
the On-Chip Debugger has an Auto-Baud Detector/Generator. After a reset, the OCD is
idle until it receives data. The OCD requires that the first character sent from the host is
the character 80H. The character 80H contains eight continuous bits Low (one Start bit
plus 7 data bits). The Auto-Baud Detector measures this period and sets the OCD Baud
Rate Generator accordingly.
Writing the DBGMODE bit in the OCD Control Register to 1 using the OCD interface.
eZ8 CPU execution of a BRK (Breakpoint) instruction (when enabled).
Match of PC to OCDCNTR register (when enabled).
OCDCNTR register decrements to 0000H (when enabled).
The DBG pin is Low when the device exits Reset.
Clearing the DBGMODE bit in the OCD Control Register to 0.
Power-on reset.
Voltage Brownout reset.
Asserting the RESET pin Low to initiate a Reset.
Driving the DBG pin Low when the device is in STOP mode initiates a System Reset.
ST = Start Bit
SP = Stop Bit
D0-D7 = Data Bits
ST
D0
Figure 59
Figure 59. OCD Data Format
D1
P R E L I M I N A R Y
D2
on page 288).
D3
D4
D5
D6
Z8 Encore! XP
D7
Product Specification
SP
®
On-Chip Debugger
F1680 Series
288
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