Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 223

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

Table 113. ESPI Mode Register (ESPIMODE)
PS025011-1010
BITS
FIELD
RESET
R/W
ADDR
ESPI Mode Register
7
The ESPI Mode register (see
the ESPI I/O pins.
SSMD—Slave Select Mode
This field selects the behavior of SS as a framing signal. For a detailed description of these
modes, see
000 = SPI Mode
When SSIO = 1, the SS pin is driven directly from the SSV bit in the Transmit Data
Command register. The Master software should set SSV (or a GPIO output if the SS pin is
not connected to the desired Slave) to the asserted state prior to or on the same clock cycle
that the transmit data register is written with the initial byte. At the end of a frame (after
the last RDRNE event), SSV will be automatically deasserted by hardware. In this mode,
SCK is active only for data transfer (one clock cycle per bit transferred).
001 = Loopback Mode
When ESPI is configured as Master (MMEN = 1), the outputs are deasserted and data is
looped from shift register out to shift register in. When ESPI is configured as a Slave
(MMEN = 0) and SS in asserts, MISO (Slave output) is tied to MOSI (Slave input) to
provide an asynchronous remote loop back (echo) function.
010 = I2S Mode (Synchronous Framing with SSV)
In this mode, the value from SSV will be output by the Master on the SS pin with one SCK
period before the data and will remain in that state until the start of the next frame.
Typically this mode is used to send back to back frames with SS alternating on each frame.
A frame boundary is indicated in the Master when SSV changes. A frame boundary is
detected in the Slave by SS changing state. The SS framing signal will lead the frame by
one SCK period. In this mode SCK will run continuously, starting with the initial SS
assertion. Frames will run back-to-back as long as software continues to provide data. An
example of this mode is the I
right channel audio data with the SS signal indicating which channel is being sent. In
SLAVE mode, the change in state of SS (Low to High or High to Low) triggers the start of
a transaction on the next SCK cycle.
SSMD
R/W
000
6
Slave Select
5
on page 194.
P R E L I M I N A R Y
2
Table
S protocol (Inter IC Sound) which is used to carry left and
R/W
4
0
113) configures the character bit width and mode of
F63H
NUMBITS[2:0]
R/W
3
0
Z8 Encore! XP
Enhanced Serial Peripheral Interface
R/W
2
0
Product Specification
SSIO
R/W
1
0
®
F1680 Series
SSPO
R/W
0
0
209