Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 214
Z8F16800144ZCOG
Manufacturer Part Number
Z8F16800144ZCOG
Description
KIT DEV FOR Z8F642 MCU 44 PIN
Manufacturer
Zilog
Series
Z8 Encore!®r
Type
MCUr
Specifications of Z8F16800144ZCOG
Contents
Hardware, Software and Documentation
For Use With/related Products
Z8F642
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4678
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®
Z8 Encore! XP
F1680 Series
Product Specification
200
accomplished by performing a word write when writing the first byte of the audio word,
which will update both the ESPI Data and Transmit Data Command words or by doing a
byte write to update SSV followed by a byte Write to the data register. The SS signal will
lead the data by one SCK period.
The transaction is terminated when the Master has no more data to transmit. After the
last bit is transferred, SCLK will stop and SS and SSV will return to their default states.
A transmit underrun error will occur at this point.
SCK (SSMD = 11,
PHASE = 0,
CLKPOL = 0)
SS
Bit0
Bit 7
MOSI, MISO
Bit7
Bit7
Bit0
frame n
frame n + 1
Figure 38. Synchronous Message Framing Mode (SSMD = 11), Multiple Frames
SPI Protocol Configuration
This section describes in detail how to configure the ESPI block for the SPI protocol. In
the SPI protocol the Master sources the SCK and asserts Slave Select signals to one or
more Slaves. The Slave Select signals are typically active Low.
SPI Master Operation
The ESPI block is configured for MASTER mode operation by setting the MMEN bit = 1
in the ESPICTL register. The SSMD field of the ESPI Mode register is set to 00 for SPI
protocol mode. The PHASE, CLKPOL, and WOR bits in the ESPICTL register and the
NUMBITS field in the ESPI Mode register must be set to be consistent with the Slave SPI
devices. Typically for an SPI Master, SSIO = 1 and SSPO = 0.
The appropriate GPIO pins are configured for the ESPI alternate function on the MOSI,
MISO and SCK pins. Typically the GPIO for the ESPI SS pin is configured in an alternate
function mode as well though the software can use any GPIO pin(s) to drive one or more
Slave select lines. If the ESPI SS signal is not used to drive a Slave select the SSIO bit
should still be set to 1 in a single Master system.
Figure 39
and
Figure 40
on page 201
display the ESPI block configured as an SPI Master.
PS025011-1010
P R E L I M I N A R Y
Enhanced Serial Peripheral Interface
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