Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 163
Z8F16800144ZCOG
Manufacturer Part Number
Z8F16800144ZCOG
Description
KIT DEV FOR Z8F642 MCU 44 PIN
Manufacturer
Zilog
Series
Z8 Encore!®r
Type
MCUr
Specifications of Z8F16800144ZCOG
Contents
Hardware, Software and Documentation
For Use With/related Products
Z8F642
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4678
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PS025011-1010
MULTIPROCESSOR Mode Receive Interrupts
When MULTIPROCESSOR (9-bit) mode is enabled, the LIN-UART processes only
frames addressed to it. To determine whether a frame of data is addressed to the
LIN-UART can be made in hardware, software or a combination of the two, depending on
the multiprocessor configuration bits. In general, the address compare feature reduces
the load on the CPU, because it does not need to access the LIN-UART when it
receives data directed to other devices on the multinode network. The following three
MULTIPROCESSOR modes are available in hardware:
1. Interrupt on all address bytes.
2. Interrupt on matched address bytes and correctly framed data bytes.
3. Interrupt only on correctly framed data bytes.
These modes are selected with
For all MULTIPROCESSOR modes, bit MPEN of the LIN-UART Control 1 Register
must be set to 1.
The first scheme is enabled by writing
address bytes cause an interrupt, while data bytes never cause an interrupt. The interrupt
service routine checks the address byte which triggered the interrupt. If it matches the
LIN-UART address, the software clears MPMD[0]. At this point, each new incoming byte
interrupts the CPU. The software determines the end of the frame and checks for it by
reading the MPRX bit of the LIN-UART Status 1 Register for each incoming byte. If
MPRX=1, a new frame begins. If the address of this new frame is different from the
LIN-UART’s address, then MPMD[0] must be set to 1 by software, causing the
LIN-UART interrupts to go inactive until the next address byte. If the new frame’s address
matches the LIN-UART’s, then the data in the new frame is also processed.
The second scheme is enabled by setting MPMD[1:0] to 10B and writing the
LIN-UART’s address into the LIN-UART Address Compare Register. This mode
introduces more hardware control, interrupting only on frames that match the
LIN-UART’s address. When an incoming address byte does not match the LIN-UART’s
address, it is ignored. All successive data bytes in this frame are also ignored. When a
matching address byte occurs, an interrupt is issued and further interrupts occur on each
successive data byte. The first data byte in the frame has
Status 1 Register. When the next address byte occurs, the hardware compares it to the
LIN-UART’s address. If there is a match, the interrupt occurs and the NEWFRM bit is set to
the first byte of the new frame. If there is no match, the LIN-UART ignores all incoming
bytes until the next address match.
The third scheme is enabled by setting
address into the LIN-UART Address Compare Register. This mode is identical to the
second scheme, except that there are no interrupts on address bytes. The first data byte of
each frame remains accompanied by a
P R E L I M I N A R Y
MPMD[1:0]
MPMD
NEWFRM
01b
to MPMD[1:0]. In this mode, all incoming
in the LIN-UART Control 1 Register.
[1:0] to
assertion.
11B
Z8 Encore! XP
NEWFRM=1
and by writing the LIN-UART’s
Product Specification
in the LIN-UART
®
F1680 Series
LIN-UART
149
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