Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 93

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

Table 40. IRQ0 Enable Low Bit Register (IRQ0ENL)
Table 42. IRQ1 Enable High Bit Register (IRQ1ENH)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS025011-1010
IRQ1 Enable High and Low Bit Registers
PA7VENH
T2ENL
R/W
R
7
0
7
0
T2ENL—Timer 2 Interrupt Request Enable Low Bit.
T1ENL—Timer 1 Interrupt Request Enable Low Bit.
T0ENL—Timer 0 Interrupt Request Enable Low Bit.
U0RENL—UART 0 Receive Interrupt Request Enable Low Bit.
U0TENL—UART 0 Transmit Interrupt Request Enable Low Bit.
I 2 CENL—I
SPIENL—SPI Interrupt Request Enable Low Bit.
ADCENL—ADC Interrupt Request Enable Low Bit.
Table 41
Bit registers (see
interrupts in the Interrupt Request 1 register. Priority is generated by setting bits in each
register.
Table 41. IRQ1 Enable and Priority Encoding
Note: x indicates the register bits from 0–7.
IRQ1ENH[x]
PA6C0ENH PA5C1ENH PAD4ENH
0
0
1
1
T1ENL
on page 79 lists the priority control for IRQ1. The IRQ1 enable High and Low
R/W
R/W
6
0
6
0
2
C Interrupt Request Enable Low Bit.
Table 42
IRQ1ENL[x] Priority
T0ENL
R/W
R/W
0
1
0
1
5
0
5
0
and
P R E L I M I N A R Y
Table 43
U0RENL
Disabled
Level 1
Level 2
Level 3
R/W
R/W
4
0
4
0
FC2H
FC4H
on page 80) form a priority encoded enabling for
PAD3ENH
U0TENL
R/W
R/W
3
0
3
0
Description
Disabled
Low
Nominal
High
PAD2ENH
Z8 Encore! XP
I2CENL
R/W
R
2
0
2
0
Product Specification
PAD1ENH
SPIENL
R/W
R
1
0
1
0
®
Interrupt Controller
F1680 Series
PA0ENH
ADCENL
R/W
R/W
0
0
0
0
79