Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 90

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

Table 36. Interrupt Request 1 Register (IRQ1)
BITS
FIELD
RESET
R/W
ADDR
PS025011-1010
Interrupt Request 1 Register
PA7VI
R/W
7
0
T2I—Timer 2 Interrupt Request
0 = No interrupt request is pending for Timer 2.
1 = An interrupt request from Timer 2 is awaiting service.
T1I—Timer 1 Interrupt Request
0 = No interrupt request is pending for Timer 1.
1 = An interrupt request from Timer 1 is awaiting service.
T0I—Timer 0 Interrupt Request
0 = No interrupt request is pending for Timer 0.
1 = An interrupt request from Timer 0 is awaiting service.
U0RXI—UART 0 Receiver Interrupt Request
0 = No interrupt request is pending for the UART 0 receiver.
1 = An interrupt request from the UART 0 receiver is awaiting service.
U0TXI—UART 0 Transmitter Interrupt Request
0 = No interrupt request is pending for the UART 0 transmitter.
1 = An interrupt request from the UART 0 transmitter is awaiting service.
I
0 = No interrupt request is pending for the I
1 = An interrupt request from I
SPII—SPI Interrupt Request
0 = No interrupt request is pending for the SPI.
1 = An interrupt request from the SPI is awaiting service.
ADCI—ADC Interrupt Request
0 = No interrupt request is pending for the ADC.
1 = An interrupt request from the ADC is awaiting service.
The Interrupt Request 1 (IRQ1) register
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ1 register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request 
to the eZ8 CPU. If interrupts are globally disabled (polled interrupts), the eZ8 CPU can
read the Interrupt Request 1 register to determine if any interrupt requests are pending.
2
CI—I
2
PA6CI
C Interrupt Request
R/W
6
0
PA5CI
R/W
5
0
P R E L I M I N A R Y
2
C is awaiting service.
PAD4I
R/W
4
0
FC3H
(Table
2
C.
PAD3I
R/W
36) stores interrupt requests for both
3
0
Z8 Encore! XP
PAD2I
R/W
2
0
Product Specification
PAD1I
R/W
1
0
®
Interrupt Controller
F1680 Series
PA0I
R/W
0
0
76