Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 201
Z8F16800144ZCOG
Manufacturer Part Number
Z8F16800144ZCOG
Description
KIT DEV FOR Z8F642 MCU 44 PIN
Manufacturer
Zilog
Series
Z8 Encore!®r
Type
MCUr
Specifications of Z8F16800144ZCOG
Contents
Hardware, Software and Documentation
For Use With/related Products
Z8F642
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4678
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Table 105. Sample Settling Time (ADCSST)
PS025011-1010
Table 106. Sample Time (ADCST)
BITS
FIELD
RESET
R/W
ADDR
Bit Position
[7:4]
[3:0]
SST
Bit Position Value (H)
[7:6]
[5:0]
ST
BITS
FIELD
RESET
R/W
ADDR
Sample Settling Time Register
Sample Time Register
0
00-3F
7
7
The Sample Settling Time Register
from the SAMPLE/HOLD signal to the START signal, when the conversion can begin.
The number of clock cycles required for settling will vary from system to system
depending on the system clock period used. The system designer should program this
register to contain the number of clocks required to meet a 0.5 µs minimum settling time.
Value (H)
0h
0h-Fh
The Sample Time Register
sample after a conversion begins by setting the START bit in the ADC Control Register or
initiated by the PWM. The number of system clock cycles required for sample time varies
from system to system, depending on the clock period used. The system designer should
program this register to contain the number of system clocks required to meet a 1.8 µs
minimum sample time.
Reserved
R/W
0
Description
Reserved—Must be 0.
Sample Hold time in number of system clock periods to meet 1.8 µs minimum.
6
6
Description
Sample settling time in number of system clock periods to meet 0.5 µs
minimum.
Reserved—Must be 0.
Reserved
R
0
5
5
1
(Table
P R E L I M I N A R Y
106) is used to program the length of active time for the
4
4
1
(Table 105)
F74H
F75H
3
1
3
1
is used to program the length of time
R/W
ST
Z8 Encore! XP
2
1
2
1
SST
R/W
Product Specification
Analog-to-Digital Converter
1
1
1
1
®
F1680 Series
0
1
0
1
187
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