Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 284
![KIT DEV FOR Z8F642 MCU 44 PIN](/photos/9/25/92529/z8f16800144zcog_sml.jpg)
Z8F16800144ZCOG
Manufacturer Part Number
Z8F16800144ZCOG
Description
KIT DEV FOR Z8F642 MCU 44 PIN
Manufacturer
Zilog
Series
Z8 Encore!®r
Type
MCUr
Specifications of Z8F16800144ZCOG
Contents
Hardware, Software and Documentation
For Use With/related Products
Z8F642
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4678
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Table 144. Flash Option Bits at Program Memory Address 0000H
Flash Option Bit Address Space
BITS
FIELD
RESET
R/W
ADDR
Note: U = Unchanged by Reset. R/W = Read/Write.
PS025011-1010
Flash Program Memory Address 0000H
WDT_RES WDT_AO
R/W
U
7
0 = Watchdog Timer timeout generates an interrupt request. Interrupts must be globally
enabled for the eZ8 CPU to acknowledge the interrupt request.
1 = Watchdog Timer timeout causes a System Reset. This setting is the default for
The first two bytes of Flash Program Memory at addresses
for the user-programmable Flash Option bits.
WDT_RES—Watchdog Timer Reset
WDT_AO—Watchdog Timer Always ON
0 = Watchdog Timer is automatically enabled upon application of system power.
1 = Watchdog Timer is enabled upon execution of the WDT instruction. Once enabled, the
OSC_SEL[1:0]—Oscillator Mode Selection
00 = On-chip oscillator configured for use with external RC networks or external
01 = Reserved.
10 = Medium power for use with medium frequency crystals or ceramic resonators
11 = Maximum power for use with high frequency crystals (8.0 MHz to 20.0 MHz).
VBO_AO—Voltage Brownout Protection Always ON
0 = Voltage Brownout Protection is disabled in STOP mode to reduce total power
unprogrammed (erased) Flash.
Watchdog Timer cannot be disabled.
Watchdog Timer can only be disabled by a Reset or Stop Mode Recovery. This setting
is the default for unprogrammed (erased) Flash.
in ACTIVE and HALT mode.
consumption. And it is controlled by VBO/LVD control bit of Power Control Register
clock input (<4 MHz).
(1 MHz to 8.0 MHz).
This setting is default for unprogrammed (erased) Flash.
R/W
U
6
R/W
OSC_SEL[1:0]
U
5
P R E L I M I N A R Y
Program Memory 0000H
R/W
U
4
VBO_AO
R/W
U
3
Z8 Encore! XP
FRP
R/W
0000H
U
2
Product Specification
and
PRAM_M
0001H
R/W
U
1
®
Flash Option Bits
F1680 Series
are reserved
FWP
R/W
U
0
270
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