Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 314

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

Table 164. OCD Control Register (OCDCTL)
.
BITS
FIELD
RESET
R/W
PS025011-1010
DBGMODE
R/W
7
0
A “reset and stop” function can be achieved by writing
go” function is achieved by writing
a “run” function is implemented by writing
DBGMODE—DEBUG Mode
Setting this bit to 1 causes the device to enter DEBUG mode. When in DEBUG mode, 
the eZ8 CPU stops fetching new instructions. Clearing this bit causes the eZ8 CPU to
resume execution. This bit is automatically set when a BRK instruction is decoded and
Breakpoints are enabled.
0 = The device is running (operating in NORMAL mode).
1 = The device is in DEBUG mode.
BRKEN—Breakpoint Enable
This bit controls the behavior of
are disabled and the
instruction is decoded, the OCD takes action depending upon the BRKLOOP bit. 
0 = BRK instruction is disabled. 
1 = BRK instruction is enabled.
DBGACK—Debug Acknowledge
This bit enables the debug acknowledge feature. If this bit is set to 1, then the OCD sends
a Debug Acknowledge character (
automatically clears itself when an acknowledge character is sent.
0 = Debug Acknowledge is disabled.
1 = Debug Acknowledge is enabled.
BRKLOOP—Breakpoint Loop
This bit determines what action the OCD takes when a BRK instruction is decoded and
breakpoints are enabled (BRKEN is 1). If this bit is 0, the DBGMODE bit is automatically
set to 1 and the OCD enters DEBUG mode. If BRKLOOP is set to 1, the eZ8 CPU loops
on the BRK instruction. 
0 = BRK instruction sets DBGMODE to 1.
1 = eZ8 CPU loops on BRK instruction.
BRKPC—Break when PC == OCDCNTR
If this bit is set to 1, then the OCDCNTR register is used as a hardware breakpoint. When
the program counter matches the value in the OCDCNTR register, DBGMODE is auto-
matically set to 1. If this bit is set, the OCDCNTR register does not count when the CPU is
running.
BRKEN
R/W
6
0
DBGACK BRKLOOP
BRK
R/W
5
0
instruction behaves like a NOP. If this bit is set to 1 and a
P R E L I M I N A R Y
BRK
R/W
FFH
4
0
41H
instruction (opcode
) to the host when a Breakpoint occurs. This bit
to this register. If the device is in DEBUG mode,
40H
BRKPC
R/W
3
0
to this register.
81H
BRKZRO
Z8 Encore! XP
00H
R/W
2
0
to this register. A “reset and
). By default, Breakpoints
Product Specification
Reserved
R/W
1
0
®
On-Chip Debugger
F1680 Series
RST
R/W
BRK
0
0
300