Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 129

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

Table 63. Timer 0–2 Status Register (TxSTAT)
PS025011-1010
BITS
FIELD
RESET
R/W
ADDR
Timer 0–2 Status Registers
NEF
R/W
7
0
PWM0UE—PWM0 Update Enable
This bit determines whether writes to the PWM0 High and Low Byte registers are 
buffered when TEN = 1. Writes to these registers are not buffered when TEN = 0 
regardless of the value of this bit.
0 = Writes to the Channel High and Low Byte registers are buffered when TEN = 1 
1 = Writes to the Channel High and Low Byte registers are not buffered 
TPOLHI—Timer Input/Output Polarity High Bit
This bit determines if timer count is triggered and captured on both edges of the input
signal. This applies only to DEMODULATION mode.
0 = Count is captured only on one edge in DEMODULATION mode. In this case, 
1 = Count is triggered on any edge and captured on both rising and falling edges of 
Reserved—Must be 0
TCLKS—Timer Clock Source
0 = System Clock
1 = Peripheral Clock
The Timer 0–2 Status (TxSTAT) indicates PWM capture/compare event occurrence, 
overrun errors, noise event occurrence and reload timeout status.
NEF—Noise Event Flag
This status is applicable only if the Timer Noise Filter is enabled. The NEF bit will be
asserted if digital noise is detected on the Timer input (TxIN) line when the data is 
being sampled (center of bit time). If this bit is set, it does not mean that the timer 
input data is corrupted (though it may be in extreme cases), just that one or more 
Noise Filter data samples near the center of the bit time did not match the average 
data value.
and only take affect on a timer reload to
when TEN = 1.
edge polarity is determined by TPOL bit in TxCTL1 register.
the Timer Input signal in DEMODULATION mode
Reserved PWM1EO PWM0EO
R/W
6
0
R/W
5
0
P R E L I M I N A R Y
F23H, F27H, F2BH
R/W
4
0
RTOEF
0001H
R/W
3
0
.
Reserved PWM1EF PWM0EF
Z8 Encore! XP
R/W
2
0
Product Specification
R/W
1
0
®
F1680 Series
R/W
0
0
Timers
115