Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 209

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

PS025011-1010
Throughput
ESPI Clock Phase and Polarity Control
Table 109. ESPI Clock Phase (
The Master sources the Serial Clock (SCK) and Slave Select signal (SS) during the
transfer.
Internal data movement (by software) to/from the ESPI block is controlled by the
Transmit Data Register Empty (TDRE) and Receive Data Register Not Empty (RDRNE)
signals. These signals are Read-only bits in the ESPI Status register. When either the
TDRE or RDRNE bits assert, an interrupt is sent to the interrupt controller. In many cases
the software application is only moving information in one direction. In this case either the
TDRE or RDRNE interrupts may be disabled to minimize software overhead.
Unidirectional data transfer is supported by setting the ESPIEN1,0 bits in the Control
Register to 10 or 01.
In MASTER mode, the maximum SCK rate supported is one-half the system 
clock frequency. This is achieved by programming the value 0001H into the Baud Rate
High/Low register pair. Though each character will be transferred at this rate it is 
unlikely that software interrupt routines could keep up with this rate. In SPI mode the
transfer will automatically pause between characters until the current receive character 
is read and the next transmit data value is written.
In SLAVE mode, the transfer rate is controlled by the Master. As long as the TDRE 
and RDRNE interrupt are serviced before the next character transfer completes, the Slave
will keep up with the Master. In SLAVE mode the baud rate must be restricted to a 
maximum of one-eighth of the system clock frequency to allow for synchronization of 
the SCK input to the internal system clock.
The ESPI supports four combinations of serial clock phase and polarity using two bits in
the ESPI Control register. The clock polarity bit, CLKPOL, selects an active High or active
Low clock and has no effect on the transfer format.
and Polarity Operation parameters. The clock phase bit, PHASE, selects one of two
fundamentally different transfer formats. The data is output a half-cycle before the receive
clock edge which provides a half cycle of setup and hold time.
PHASE
0
0
1
1
CLKPOL
0
1
0
1
SCK Transmit Edge
P R E L I M I N A R Y
PHASE
Falling
Falling
Rising
Rising
) and Clock Polarity (
SCK Receive Edge
Table 109
Z8 Encore! XP
Falling
Falling
Rising
Rising
Enhanced Serial Peripheral Interface
lists the ESPI Clock Phase
CLKPOL
Product Specification
) Operation
SCK Idle State
®
F1680 Series
High
High
Low
Low
195