Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 220
Z8F16800144ZCOG
Manufacturer Part Number
Z8F16800144ZCOG
Description
KIT DEV FOR Z8F642 MCU 44 PIN
Manufacturer
Zilog
Series
Z8 Encore!®r
Type
MCUr
Specifications of Z8F16800144ZCOG
Contents
Hardware, Software and Documentation
For Use With/related Products
Z8F642
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4678
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Table 110. ESPI Data Register (ESPIDATA)
Table 111. ESPI Transmit Data Command and Receive Data Buffer Control Register (ESPITDCR)
PS025011-1010
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
ESPI Transmit Data Command and Receive Data
Buffer Control Register
CRDR
R/W
R/W
7
X
7
0
DATA—Data
Transmit and/or receive data. Writes to the ESPIDATA register load the shift register.
Reads from the ESPIDATA register return the value of the receive data register.
The ESPI Transmit Data Command and Receive Data Buffer Control register
(Table
mode), clear receive data buffer function and flag. The CRDR, TEOF, and SSV bits can be
controlled by a bus write to this register.
CRDR—Clear Receive Data Register
Writing 1 to this bit is used to clear all data in receive data buffer.
RDFLAG—Receive Data Buffer FLAG
This bit is used to indicate how many bytes stored in receive buffer.
00 = 0 or 4 bytes (see RDRNE in ESPI Status Register).
01 = 1 byte.
02 = 2 bytes.
03 = 3 bytes.
111) provides control of the SS pin when it is configured as an output (MASTER
R/W
X
6
6
RDFLAG
00
R
R/W
X
5
5
P R E L I M I N A R Y
R/W
X
R
4
4
0
DATA
F60H
F61H
R/W
R
X
3
3
0
Z8 Encore! XP
Enhanced Serial Peripheral Interface
R/W
X
R
2
2
0
Product Specification
TEOF
R/W
R/W
X
1
1
0
®
F1680 Series
R/W
SSV
R/W
X
0
0
0
206
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