HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 153

MPU 1.5/3.3V 0K PB-FREE 256-BGA

HD6417712BPV

Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet

Specifications of HD6417712BPV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Table 3.16 DSR Register Bits
Bits
31 to
12
11 to 9 TS2 to TS0 All 0
8
7
6
Bit Name
TC
GT
Z
Initial
Value
All 0
0
0
0
R/W
R
R/W
R/W
R/W
R/W
Function
These bits are always read as 0. The write value
should always be 0.
Specifies the operation result status to be set in the T
bit in the SR register if the TC bit is 1. If the S bit of
the SR register is set to 1, an overflow is detected.
000: Carry/borrow mode
001: Negative value mode
010: Zero mode
011: Overflow mode
100: Signed greater mode
101: Signed greater than or equal to mode
110: Reserved (setting prohibited)
111: Reserved (setting prohibited)
TC Bit
0: The T bit of the SR register is not affected by the
1: The T bit of the SR register changes according to
Signed Greater Bit
Indicates that the operation result is positive (except
0), or that operand 1 is greater than operand 2
1: Operation result is positive, or operand 1 is greater
Zero Bit
Indicates that the operation result is zero (0), or that
operand 1 is equal to operand 2
1: Operation result is zero (0), or operands are equal
Reserved Bits
T Bit Status Selection
DSP instruction.
the TS bit of the DSR register while the DSP
instruction is executed. Note, however, the T bit
does not change during conditional DSP instruction
execution.
than operand 2
Rev. 1.00 Dec. 27, 2005 Page 109 of 1044
Section 3 DSP Operating Unit
REJ09B0269-0100

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