HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 776

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
19.2.3
EDRRR is a 32-bit readable/writable register that issues receive directives to the E-DMAC. After
writing 1 to the RR bit in this register, the E-DMAC reads the receive descriptor at the address
specified by RDLAR. If the RACT bit of this descriptor is set to 1 (valid), and the receive FIFO
holds a receive frame, the E-DMAC starts receive DMA transfer. When DMA transfer based on
the first receive descriptor is completed, the E-DMAC reads the next receive descriptor. If the
RACT bit of that descriptor is set to 1 (valid), the E-DMAC continues receive DMA operation.
However, if the receive FIFO holds no receive data, the E-DMAC places receive DMA operation
in the standby state. If the RACT bit of the receive descriptor is cleared to 0 (invalid), the E-
DMAC clears the RR bit and stops receive DMAC operation.
For details of writing to the RR bit, see section 19.4.1, Using of EDTRR and EDRRR.
Rev. 1.00 Dec. 27, 2005 Page 732 of 932
REJ09B0269-0100
Bit
31 to 1
0
E-DMAC Receive Request Register (EDRRR)
Bit Name

TR
Initial
Value
All 0
0
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Transmit Request
0: Transmission-halted state. Writing 0 does not stop
1: Transmit DMA operation being performed by the E-
transmission. Termination of transmission is
controlled by the TACT bit of the transmit
descriptor.
DMAC. After writing 1 to this bit, the E-DMAC
starts reading a transmit descriptor.