HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 222

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 4 Exception Handling
CPU Address Error in Repeat Control Period: If a CPU address error occurs in the repeat
control period, the exception is accepted but an exception code (H'070) indicating the repeat loop
period is specified in the EXPEVT. If a CPU address error occurs in instructions following a
repeat detection instruction to repeat end instruction, an exception code for instruction access or
data access is specified in the EXPEVT.
The SPC is saved according to the description in section 4.4.3, Exception in Repeat Control
Period.
After the CPU address error exception processing, the repeat control cannot be returned correctly.
To execute a repeat loop correctly, care must be taken not to generate a CPU address error in the
repeat control period.
Note: In a repeat loop consisting of one to three instructions, some restrictions apply to repeat
Table 4.5
Note: The following labels are used here.
Rev. 1.00 Dec. 27, 2005 Page 178 of 932
REJ09B0269-0100
Instruction where
Exception Occurs
RptDtct
RptDtct1
RptDtct2
RptDtct3
RptDtct:
RptDtct1: An instruction of one instruction following the repeat detection instruction
RptDtct2:
RptDtct3:
detection instructions and all the remaining instructions. In a repeat loop consisting of four
or more instructions, restrictions apply to only the four instructions that include a repeat
end instruction. The restriction occurs when SR.RC[11:0] ≥ 1.
Instruction Where a Specific Exception Occurs when Memory Access Exception
Occurs in Repeat Control (SR.RC[11:0] ≥ 1)
Repeat detection instruction
An instruction of two instruction following the repeat detection instruction
An instruction of three instruction following the repeat detection instruction
1
Instruction/data
access


Number of Instructions in Repeat Loop
2
Instruction/data
access
Instruction/data
access

Instruction/data
access
Instruction/data
access
Instruction/data
access
3
4 or Greater
Instruction/data
access
Instruction/data
access
Instruction/data
access