HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 645

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

17.3.7
SIFCTR is used to indicate the area available for the transmit/receive FIFO transfer. SIFCTR is
initialized by a power-on reset or software reset.
Bit
15
14
13
12
11
10
9
8
Bit Name
TFWM2
TFWM1
TFWM0
TFUA4
TFUA3
TFUA2
TFUA1
TFUA0
SIOF FIFO Control Register (SIFCTR)
Initial
Value
0
0
0
1
0
0
0
0
R/W
R/W
R/W
R/W
R
R
R
R
R
Description
Transmit FIFO Watermark
A transfer request to the transmit FIFO is issued by the TDREQ
bit in SISTR. The transmit FIFO is always used as 16 stages of
FIFO regardless of these bit settings.
000: Issue a transfer request when 16 stages of transmit FIFO
001: Reserved (setting prohibited)
010: Reserved (setting prohibited)
011: Reserved (setting prohibited)
100: Issue a transfer request when 12 or more stages of
101: Issue a transfer request when 8 or more stages of
110: Issue a transfer request when 4 or more stages of
111: Issue a transfer request when 1 or more stages of
Transmit FIFO Usable Area
Indicate the number of words that can be transferred by the
CPU or DMAC as B′00000 to B′10000.
are empty.
transmit FIFO are empty.
transmit FIFO are empty.
transmit FIFO are empty.
transmit FIFO are empty.
Rev. 1.00 Dec. 27, 2005 Page 601 of 932
Section 17 Serial I/O with FIFO (SIOF)
REJ09B0269-0100