HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 214

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 4 Exception Handling
• Save address
• Exception code
• Remarks
TLB invalid exception:
• Conditions
• Types
• Save address
• Exception code
• Remarks
TLB protection exception:
• Conditions
• Types
Rev. 1.00 Dec. 27, 2005 Page 170 of 932
REJ09B0269-0100
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
An exception occurred during read: H′040
An exception occurred during write: H′060
The logical address (32 bits) that caused the exception is set in TEA and the MMU registers
are updated. The vector address of the TLB miss exception becomes VBR + H'0400. To speed
up TLB miss processing, the offset differs from other exceptions.
Comparison of TLB addresses shows address match but V = 0.
Instruction synchronous, re-execution type
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
An exception occurred during read: H′040
An exception occurred during write: H′060
The logical address (32 bits) that caused the exception is set in TEA and the MMU registers
are updated.
When a hit access violates the TLB protection information (PR bits).
Instruction synchronous, re-execution type