HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 586

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 16 Serial Communication Interface with FIFO (SCIF)
Rev. 1.00 Dec. 27, 2005 Page 542 of 932
REJ09B0269-0100
Bit
6
5
Bit Name
RIE
TE
Initial
Value
0
0
R/W
R/W
R/W
Description
Receive Interrupt Enable
Enables or disables generation of a receive-data-full
interrupt (RXI) request when the RDF flag or DR flag
in SCFSR is set to 1, receive-error interrupt (ERI)
request when the ER flag in SCFSR is set to 1, or
break-interrupt (BRI) request when the BRK flag in
SCFSR or the ORER flag in SCLSR is set to 1.
0: Receive-data-full interrupt (RXI) request, receive-
1: Receive-data-full interrupt (RXI) request, receive-
Note: * An RXI request can be cleared by reading 1
Transmit Enable
Enables or disables the start of serial transmission by
the SCIF.
0: Transmission disabled
1: Transmission enabled*
Note: * SCSMR and SCFCR settings must be
error interrupt (ERI) request, and break-interrupt
(BRI) request disabled*
error interrupt (ERI) request, and break-interrupt
(BRI) request enabled
from the RDF flag or DR flag, then clearing
the flag to 0, or by clearing the RIE bit to 0.
The ERI and BRI requests can be cleared
by reading 1 from the ER, BRK, or ORER
flag, then clearing the flag to 0, or clearing
the RIE and REIE bits to 0.
made, the transmit format decided, and the
transmit FIFO reset, before the TE bit is set
to 1.