HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 182

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 3 DSP Operating Unit
3.5.12
The DSP unit of this LSI provides additional two independent registers, MACL and MACH, in
order to support CPU standard multiply/MAC operations. They can be also used as temporary
storage registers by local data move instructions between MACH/L and other DSP registers.
Figure 3.22 shows the flow of seven local data move instructions. Table 3.33 shows the variation
of this type of instruction.
Table 3.33 Variation of Local Data Move Operations
This instruction is very similar to other transfer instructions. If either the A0 or A1 register is
specified as the destination operand of PSTS, the signed bit is sign-extended and copied into the
corresponding guard-bit parts, A0G or A1G. The DC bit in DSR and other condition code bits are
not updated regardless of the instruction result. This instruction can operate as a conditional. This
instruction can operate with MOVX and MOVY in parallel.
Rev. 1.00 Dec. 27, 2005 Page 138 of 1044
REJ09B0269-0100
Mnemonic
PLDS
PSTS
Local Data Move Instruction
Function
Data move from DSP register to MACL/MACH
Data move from MACL/MACH to DSP register
Figure 3.22 Local Data Move Instruction Flow
PSTS
M0
X0
Y0
A0
MACH
MACL
A0G
M1
X1
Y1
A1
Cannot be used
PLDS
A1G
DSR
Operand
Dz
Dz