HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 537

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13.5
When using the DMAC, note the following:
Note on Using TEND Pin:
If a DMA transfer is performed under one of the conditions described below and, after completion
of the transfer, retransfer is performed on the same channel, the TEND pin is asserted once in the
first DMA transfer in retransfer when the retransfer condition satisfies (1) DACK is output in a
dual address mode read cycle (with the AM bit in CHCR cleared to 0) and the DMA transfer
source address (SAR) is in external memory space or (2) in single address mode.
Conditions:
• DACK is output in a dual address mode read cycle (with the AM bit in CHCR cleared to 0)
• DACK is output in a dual address mode write cycle (with the AM bit in CHCR set to 1) and
• Single address mode
Method of Avoidance:
Perform a dummy DMA transfer under one of the settings below. After start of a dummy DMA
transfer, clear all bits in the DMA channel control register (CHCR) of the corresponding channel
to suspend the dummy DMA transfer forcibly.
• DACK is output in a dual address mode read cycle (with the AM bit in CHCR cleared to 0)
• DACK is output in a dual address mode write cycle (with the AM bit in CHCR set to 1) and
and the DMA transfer source address (SAR) is in external memory space.
the DMA transfer destination address (DAR) is in external memory space.
and the DMA transfer source address (SAR) is in external memory space.
the DMA transfer destination address (DAR) is in external memory space.
Usage Note
Section 13 Direct Memory Access Controller (DMAC)
Rev. 1.00 Dec. 27, 2005 Page 493 of 932
REJ09B0269-0100