HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 21

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 Direct Memory Access Controller (DMAC) ...................................459
13.1 Features.............................................................................................................................. 459
13.2 Input/Output Pins ............................................................................................................... 461
13.3 Register Descriptions ......................................................................................................... 462
13.4 Operation ........................................................................................................................... 474
13.5 Usage Note......................................................................................................................... 493
Section 14 Timer Unit (TMU) ...........................................................................495
14.1 Features.............................................................................................................................. 495
14.2 Register Descriptions ......................................................................................................... 497
14.3 TMU Operation.................................................................................................................. 500
14.4 Interrupts............................................................................................................................ 503
14.5 Usage Notes ....................................................................................................................... 504
Section 15 Realtime Clock (RTC) .....................................................................505
15.1 Feature ............................................................................................................................... 505
15.2 Input/Output Pins ............................................................................................................... 507
15.3 Register Descriptions ......................................................................................................... 507
13.3.1 DMA Source Address Register (SAR) ................................................................. 463
13.3.2 DMA Destination Address Register (DAR) ......................................................... 463
13.3.3 DMA Transfer Count Register (DMATCR) ......................................................... 464
13.3.4 DMA Channel Control Register (CHCR) ............................................................. 464
13.3.5 DMA Operation Register (DMAOR) ................................................................... 469
13.3.6 DMA Extension Resource Selector 0 to 2 (DMARS0 to DMARS2) ................... 471
13.4.1 DMA Transfer Flow ............................................................................................. 474
13.4.2 DMA Transfer Requests ....................................................................................... 477
13.4.3 Channel Priority.................................................................................................... 479
13.4.4 DMA Transfer Types............................................................................................ 482
13.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing ........................... 489
14.1.1 Block Diagram...................................................................................................... 495
14.2.1 Timer Start Register (TSTR) ................................................................................ 497
14.2.2 Timer Control Registers (TCR) ............................................................................ 498
14.2.3 Timer Constant Registers (TCOR) ....................................................................... 499
14.2.4 Timer Counters (TCNT) ....................................................................................... 499
14.3.1 Counter Operation................................................................................................. 500
14.4.1 Status Flag Set Timing.......................................................................................... 503
14.4.2 Status Flag Clear Timing ...................................................................................... 503
14.4.3 Interrupt Sources and Priorities ............................................................................ 504
14.5.1 Writing to Registers .............................................................................................. 504
14.5.2 Reading Registers ................................................................................................. 504
Rev. 1.00 Dec. 27, 2005 Page xix of xlii