HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 653

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

17.3.10 Serial Transmit Data Register (SITDR)
SITDR is used to specify the SIOF transmit data. The setting data for this register is stored in the
transmit FIFO. SITDR is initialized by a power-on reset, software reset, or transmit reset.
Bit
31 to 16
15 to 0
Bit Name
SITDL15 to
SITDL0
SITDR15 to
SITDR0
Initial
Value
All 0
All 0
R/W
W
W
Description
Left Channel Transmit Data
Specify data to be output from the TXD_SIO pin as left
channel data. The position of the left channel data in the
transmission frame is specified by the TDLA bit in
SITDAR.
These bits are valid only when the TDLE bit in SITDAR is
set to 1.
Right Channel Transmit Data
Specify data to be output from the TXD_SIO pin as right
channel data. The position of the right channel data in the
transmission frame is specified by the TDRA bit in
SITDAR.
These bits are valid only when the TDLE bit and TLREP
bit in SITDAR are set to 1 and cleared to 0, respectively.
Rev. 1.00 Dec. 27, 2005 Page 609 of 932
Section 17 Serial I/O with FIFO (SIOF)
REJ09B0269-0100