HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 636

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 17 Serial I/O with FIFO (SIOF)
Rev. 1.00 Dec. 27, 2005 Page 592 of 932
REJ09B0269-0100
Bit
11
10
9
8
7
6
5
Bit Name
FL3
FL2
FL1
FL0
TXDIZ
LSBF
RCIM
Initial
Value
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Frame Length
00xx: Slot length is 8 bits and frame length is 8 bits
0100: Slot length is 8 bits and frame length is 16 bits
0101: Slot length is 8 bits and frame length is 32 bits
0110: Slot length is 8 bits and frame length is 64 bits
0111: Slot length is 8 bits and frame length is 128 bits
10xx: Slot length is 16 bits and frame length is 16 bits
1100: Slot length is 16 bits and frame length is 32 bits
1101: Slot length is 16 bits and frame length is 64 bits
1110: Slot length is 16 bits and frame length is 128 bits
1111: Slot length is 16 bits and frame length is 256 bits
Notes: 1. When slot length is specified as 8 bits, control
High-Impedance Output when Transmission is Invalid
Specifies high-impedance output when transmission is
invalid.
0: High output (1 output) when invalid
1: High-impedance output when invalid
Note: Invalid means when disabled, and when a slot that
LSB-First Transmission/Reception
Selects the bit order of a transmit/receive frame.
0: MSB-first
1: LSB-first
Receive Control Data Interrupt Mode
Selects the set timing of the RCRDY bit in SISTR.
0: Sets the RCRDY bit in SISTR when the contents of
1: Sets the RCRDY bit in SISTR each time when SIRCR
SIRCR change.
receives control data.
is not assigned as transmit data or control data is
being transmitted.
x: Don't care
2. When LSB is first transmitted or received,
data cannot be transmitted or received.
control data cannot be transmitted or received.