HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 478

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 12 Bus State Controller (BSC)
that if an access occurs in power-down mode, a cycle of overhead occurs because a cycle that
asserts the CKE in order to cancel power-down mode is inserted.
Figure 12.28 shows the access timing in power-down mode.
Power-On Sequence: In order to use synchronous DRAM, mode setting must first be performed
after powering on. To perform synchronous DRAM initialization correctly, the bus state controller
registers must first be set, followed by a write to the synchronous DRAM mode register. In
synchronous DRAM mode register setting, the address signal value at that time is latched by a
combination of the CSn, RAS, CAS, and RD/WR signals. If the value to be set is X, the bus state
controller provides for value X to be written to the synchronous DRAM mode register by
performing a write to address H'A4FD4000 + X for area 2 synchronous DRAM, and to address
H'A4FD5000 + X for area 3 synchronous DRAM. In this operation the data is ignored, but the
mode write is performed as a byte-size access. To set burst read/single write, CAS latency 2 to 3,
Rev. 1.00 Dec. 27, 2005 Page 434 of 932
REJ09B0269-0100
A12/A11*
A25 to A0
D31 to D0
DACKn*
RD/WR
DQMxx
CKIO
CKE
RAS
CAS
CSn
BS
1
2
Power-down
Notes: 1.Address pin to be connected to the A10 pin of SDRAM.
Figure 12.28 Access Timing in Power-Down Mode
2. The waveform for DACKn is when active low is specified.
Tnop
Tr
Tc1
Td1
Tde
Tap
Power-down