HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 311

MPU 1.5/3.3V 0K PB-FREE 256-BGA

HD6417712BPV

Manufacturer Part Number
HD6417712BPV
Description
MPU 1.5/3.3V 0K PB-FREE 256-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH Ethernetr
Datasheet

Specifications of HD6417712BPV

Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, FIFO, SCI, SIO
Peripherals
DMA, POR, WDT
Number Of I /o
24
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417712BPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
9.2.2
BAMRA is a 32-bit readable/writable register. BAMRA specifies bits masked in the break address
specified by BARA.
9.2.3
BBRA is a 16-bit readable/writable register, which specifies (1) L bus cycle or I bus cycle, (2)
instruction fetch or data access, (3) read or write, and (4) operand size in the break conditions of
channel A.
Bit
31 to 0
Bit
15 to 8
7
6
Break Address Mask Register A (BAMRA)
Break Bus Cycle Register A (BBRA)
Bit Name
CDA1
CDA0
Bit Name
BAMA31 to
BAMA 0
Initial
Value
All 0
Initial
Value
All 0
0
0
R/W
R/W
R/W
R
R/W
R/W
Description
Break Address Mask A
Specify bits masked in the channel A break address
bits specified by BARA (BAA31–BAA0).
0: Break address bit BAAn of channel A is included in
1: Break address bit BAAn of channel A is masked and
Note:
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
L Bus Cycle/I Bus Cycle Select A
Select the L bus cycle or I bus cycle as the bus cycle of
the channel A break condition.
00: Condition comparison is not performed
01: The break condition is the L bus cycle
10: The break condition is the I bus cycle
11: The break condition is the L bus cycle
the break condition
is not included in the break condition
n = 31 to 0
Rev. 1.00 Dec. 27, 2005 Page 267 of 932
Section 9 User Break Controller
REJ09B0269-0100

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