HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 681

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

This LSI has an on-chip Ethernet controller (EtherC) conforming to the Ethernet or the IEEE802.3
MAC (Media Access Control) layer standard. Connecting a physical-layer LSI (PHY-LSI)
complying with this standard enables the Ethernet controller (EtherC) to perform transmission and
reception of Ethernet/IEEE802.3 frames. The LSI has two MAC layer interface ports (hereafter
referred to as port 0 and port 1), both of which can be made to perform transmission and reception
independently. This Ethernet controller also has an on-chip TSU (Transfer Switching Unit) which
controls transferring, allowing mutual transfer of data between MAC layer controllers of ports 0
and 1. This TSU has a 32-entry CAM (Content Addressable Memory) and two external CAM
interface input pins for determining whether to receive or transfer packets input to both Ethernet
controllers. The TSU also has a total 6-kbyte transfer FIFO for retaining packets to be transferred,
allowing allocation of transfer FIFO capacity to be set freely for the transfer conditions of port 0 to
1 and port 1 to 0. The Ethernet controller is connected to the Ethernet Direct Memory Access
Controller (E-DMAC) for Ethernet controller inside the LSI, and carries out high-speed data
transfer to and from the memory.
Figure 18.1 shows a configuration of the EtherC.
18.1
• Transmission and reception of Ethernet/IEEE802.3 frames
• Supports 10/100 Mbps receive/transfer
• Supports full-duplex and half-duplex modes
• Conforms to IEEE802.3u standard MII (Media Independent Interface)
• Magic Packet detection and Wake-On-LAN (WOL) signal output
• Ethernet frame relay function by the TSU
• Qtag addition and deletion functions conforming to IEEE802.1Q specifications (when frame
• MAC address filtering function by the multicast (group) address
• Ethernet frame receive and transfer control functions by the CAM (Content Addressable
ISFETH01B_000020020900
relay is performed by the TSU)
Memory) interface signals input externally
Features
Section 18 Ethernet Controller (EtherC)
Rev. 1.00 Dec. 27, 2005 Page 637 of 932
Section 18 Ethernet Controller (EtherC)
REJ09B0269-0100