HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 815

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19.3.4
(1)
If an error occurs during multi-buffer frame transmission, the processing shown in figure 19.6 is
carried out by the E-DMAC.
In the figure where the transmit descriptor is shown as inactive (TACT bit = 0), buffer data has
already been transmitted normally, and where the transmit descriptor is shown as active (TACT bit
= 1), buffer data has not been transmitted. If a frame transmit error occurs in the first descriptor
part where the transmit descriptor is active (TACT bit = 1), transmission is halted, and the TACT
bit cleared to 0, immediately. The next descriptor is then read, and the position within the transmit
frame is determined on the basis of bits TFP1 and TFP0 (continuing [B′00] or end [B′01]). In the
case of a continuing descriptor, the TACT bit is cleared to 0, only, and the next descriptor is read
immediately. If the descriptor is the final descriptor, not only is the TACT bit cleared to 0, but
write-back is also performed to the TFE and TFS bits at the same time. Data in the buffer is not
transmitted between the occurrence of an error and write-back to the final descriptor. If error
interrupts are enabled in the EtherC/E-DMAC status interrupt permission register (EESIPR), an
interrupt is generated immediately after the final descriptor write-back.
E-DMAC
Multi-Buffer Frame Transmit Processing
Inactivates TACT and writes TFE, TFS
Inactivates TACT (change 1 to 0)
Transmit/Receive Processing of Multi-Buffer Frame (Single-Frame/
Multi-Descriptor)
Descriptor read
Descriptor read
Descriptor read
Descriptor read
Figure 19.6 E-DMAC Operation after Transmit Error
Inactivates TACT
Inactivates TACT
Inactivates TACT
Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
C
T
A
T
0
0
0
1
1
1
1
1
1
D
E
T
L
0
0
0
0
0
0
0
0
1
Descriptors
P
T
F
1
1
0
0
0
0
0
0
0
1
T
F
P
0
0
0
0
0
0
0
0
1
0
Continue
Continue
Continue
Continue
Continue
Continue
Frame
Type
Start
Start
End
Rev. 1.00 Dec. 27, 2005 Page 771 of 932
Untransmitted
data is not
transmitted
after error
occurrence.
Descriptor is
only processed.
One frame
REJ09B0269-0100
Buffer length set
by descriptor
Transmit error
occurrence
Transmitted data
Untransmitted data