HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 30

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 4 Exception Handling
Figure 4.1 Register Bit Configuration ........................................................................................ 156
Section 5 Memory Management Unit (MMU)
Figure 5.1 MMU Functions ........................................................................................................ 183
Figure 5.2 Virtual Address Space (MMUCR.AT = 1)................................................................ 185
Figure 5.3 Virtual Address Space (MMUCR.AT = 0)................................................................ 186
Figure 5.4 P4 Area...................................................................................................................... 187
Figure 5.5 External Memory Space ............................................................................................ 188
Figure 5.6 Overall Configuration of the TLB............................................................................. 193
Figure 5.7 Virtual Address and TLB Structure........................................................................... 194
Figure 5.8 TLB Indexing (IX = 1) .............................................................................................. 195
Figure 5.9 TLB Indexing (IX = 0) .............................................................................................. 196
Figure 5.10 Objects of Address Comparison.............................................................................. 197
Figure 5.11 Operation of LDTLB Instruction............................................................................. 202
Figure 5.12 Synonym Problem (32-kbyte Cache) ...................................................................... 204
Figure 5.13 MMU Exception Generation Flowchart .................................................................. 210
Figure 5.14 Specifying Address and Data for Memory-Mapped TLB Access ........................... 212
Section 6 Cache
Figure 6.1 Cache Structure ......................................................................................................... 215
Figure 6.2 Cache Search Scheme ............................................................................................... 223
Figure 6.3 Write-Back Buffer Configuration.............................................................................. 225
Figure 6.4 Specifying Address and Data for Memory-Mapped Cache Access
Figure 6.5 Specifying Address and Data for Memory-Mapped Cache Access
Section 8 Interrupt Controller (INTC)
Figure 8.1 Block Diagram of INTC............................................................................................ 236
Figure 8.2 Example of IRL Interrupt Connection....................................................................... 239
Figure 8.3 Interrupt Operation Flowchart................................................................................... 261
Section 9 User Break Controller
Figure 9.1 Block Diagram of User Break Controller.................................................................. 265
Section 10 Power-Down Modes
Figure 10.1 Canceling Standby Mode with STBCR.STBY........................................................ 305
Figure 10.2 STATUS Output at Power-On Reset....................................................................... 306
Figure 10.3 STATUS Output at Manual Reset........................................................................... 307
Figure 10.4 STATUS Output when Software Standby Mode is Canceled by Interrupt ............. 307
Figure 10.5 STATUS Output when Software Standby Mode is Canceled by
Rev. 1.00 Dec. 27, 2005 Page xxviii of xlii
(16 kbytes mode)...................................................................................................... 228
(32 kbytes mode)...................................................................................................... 229
Power-on Reset ....................................................................................................... 308