HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 36

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Figure 24.8 Oscillation Settling Time at Standby Return
Figure 24.9 PLL Synchronization Settling Time by Reset or NMI ............................................ 863
Figure 24.10 PLL Synchronization Settling Time by IRQ/IRL Interrupts ................................. 864
Figure 24.11 PLL Synchronization Settling Time when Frequency Multiplication
Figure 24.12 Reset Input Timing................................................................................................ 866
Figure 24.13 Interrupt Signal Input Timing................................................................................ 866
Figure 24.14 Bus Release Timing .............................................................................................. 866
Figure 24.15 Pin Drive Timing at Standby................................................................................. 867
Figure 24.16 IRQOUT Output Delay Time................................................................................ 867
Figure 24.17 Basic Bus Cycle (No Wait) ................................................................................... 870
Figure 24.18 Basic Bus Cycle (One Software Wait) .................................................................. 871
Figure 24.19 Basic Bus Cycle (One External Wait) ................................................................... 872
Figure 24.20 Basic Bus Cycle (One Software Wait, External Wait Enabled (WM bit = 0),
Figure 24.21 Burst ROM Read Cycle (One Access Wait, One External Wait,
Figure 24.22 Synchronous DRAM Single Read Bus Cycle (Auto Precharge,
Figure 24.23 Synchronous DRAM Single Read Bus Cycle (Auto Precharge,
Figure 24.24 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4),
Figure 24.25 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4),
Figure 24.26 Synchronous DRAM Single Write Bus Cycle
Figure 24.27 Synchronous DRAM Single Write Bus Cycle
Figure 24.28 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4),
Figure 24.29 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4),
Figure 24.30 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
Figure 24.31 Synchronous DRAM Burst Read Bus Cycle (Single Read × 4)
Rev. 1.00 Dec. 27, 2005 Page xxxiv of xlii
(Return by IRQ5 to IRQ0 and IRL3 to IRL0)......................................................... 863
Ratio Modified...................................................................................................... 864
No Idle Cycle Setting) .......................................................................................... 873
One Burst Wait, Two Bursts)................................................................................ 874
CAS Latency = 2, TRCD = 1 Cycle, TRP = 1 Cycle)........................................... 875
CAS Latency = 2, TRCD = 2 Cycle, TRP = 2 Cycle)........................................... 876
(Auto Precharge, CAS Latency = 2, TRCD = 1 Cycle, TRP = 2 Cycle)............... 877
(Auto Precharge, CAS Latency = 2, TRCD = 2 Cycle, TRP = 1 Cycle)............... 878
(Auto Precharge, TRWL = 2 Cycle) ..................................................................... 879
(Auto Precharge, TRCD = 3 Cycle, TRWL = 2 Cycle) ........................................ 880
(Auto Precharge, TRCD = 1 Cycle, TRWL = 2 Cycle) ........................................ 881
(Auto Precharge, TRCD = 2 Cycle, TRWL = 2 Cycle) ........................................ 882
(Bank Active Mode, ACTV + READ Commands, CAS Latency = 2,
TRCD = 1 Cycle) .................................................................................................. 883
(Bank Active Mode, READ Command, Same Row Address,
CAS Latency = 2, TRCD = 1 Cycle) .................................................................... 884