HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 349

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

• Canceling with a Reset
Software standby mode is canceled by a reset (power-on or manual). Keep the RESETP or
RESETM pin low until the clock oscillation settles. The internal clock will continue to be output
to the CKIO pin.
10.3.3
Transition to Module Standby Function: Setting each MSTP bit in the standby control registers
to 1 halts the supply of clocks to the corresponding on-chip peripheral modules. This function can
be used to reduce the power consumption in normal or sleep mode. Before a transition is made, the
module should be disabled.
In the module standby state, the functions of the external pins of the on-chip peripheral modules
change depending on the on-chip peripheral module. For details, see section 1, Overview and Pin
Function. All of the register states are the same as those in standby mode. For details, see table
10.3.
Canceling Module Standby Function: The module standby function can be canceled by clearing
the MSTP bits to 0, or by a power-on reset.
To cancel the module standby function by clearing the corresponding MSTP bit to 0, read the
MSTP bit to check the MSTP bit was cleared correctly.
WTCNT value
H'FF
H'80
Module Standby Function
Figure 10.1 Canceling Standby Mode with STBCR.STBY
Interrupt
request
Crystal resonator settling
time and PLL synchronization
time
Rev. 1.00 Dec. 27, 2005 Page 305 of 932
WDT overflow and branch to
interrupt handling routine
Clear bit STBCR.STBY before
WTCNT reaches H'80. When
STBCR. STBY is cleared, WTCNT
halts automatically.
Section 10 Power-Down Modes
REJ09B0269-0100
Time