HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 705

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

18.3.25 Relay FIFO Overflow Alert Set Register (Port 0) (TSU_BSYSL0)
The TSU has an alert function, which informs the MAC-0 and MAC-1 that writing to the TSU
FIFO will be disabled when the data volume written in the TSU FIFO during relay operations
exceeds a certain threshold. TSU_BSYSL0 sets the threshold of the TSU FIFO when the TSU
alerts the MAC-0 that writing to the TSU FIFO will be disabled during relay operations.
Bit
31 to 6 
5 to 0
Bit Name
BSYSL05 to
BSYSL00
Initial
Value
All 0
All 1
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Sets the threshold of the port 0 to 1 TSU FIFO
capacity in 256-byte units when the TSU alerts the
MAC-0 that writing in the TSU FIFO will be disabled
during relay operations.
H′00: 0 byte
H′01: 256 bytes
H′02: 512 bytes
H′16: 5632 bytes
H′17: 5888 bytes
Settings are disabled for H′18 to H′3F. (Alert is not
always carried out.)
When H′00 is set, the TSU always alerts the MAC-0
that writing to the TSU FIFO will be disabled. When
the value set is above the port 0 to 1 transfer FIFO
capacity set by the FCM2 to FCM0 in TSU_FCM, the
TSU does not alert the MAC-0 that writing to the TSU
FIFO will be disabled.
Writing to this register is prohibited, after relay
operations have been enabled once (after the
FWEN0 in TSU_FWEN0 or the FWEN1 in
TSU_FWEN1 is set to 1).
When the enable bit of relay operations (the FWEN0
in TSU_FWEN0 or the FWEN1 in TSU_FWEN1) is
cleared to 0, the TSU stops alerting the MAC-0 that
writing to the TSU FIFO will be disabled.
:
:
Rev. 1.00 Dec. 27, 2005 Page 661 of 932
Section 18 Ethernet Controller (EtherC)
REJ09B0269-0100