HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 665

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Control by Secondary FS (Slave Mode 2): The CODEC normally outputs SIOFSYNC as
synchronization pulse (FS). In this method, the CODEC outputs the secondary FS specific to the
control data transfer after 1/2 frame time has been passed (not the normal FS output timing) to
transmit or receive control data. This method is valid for SIOF slave mode. The following
summarizes the control data interface procedure by secondary FS.
• Transmit normal transmit data of LSB = 0 (The SIOF forcibly clears 0)
• To execute control data transmission, send transmit data of LSB = 1 (The SIOF forcibly set to
• The CODEC outputs the secondary FS.
• The SIOF transmits control data (data specified by SITCR) or receives control data (stores in
Figure 17.8 shows an example of control data interface timing by secondary FS.
17.4.6
Overview: The transmit and receive FIFOs of the SIOF have the following features.
• Sixteen-stage 32-bit FIFOs for transmission and reception
• The FIFO pointer can be modified in one read or write cycle regardless of access size of the
• Regardless of access size, the number of access cycles is always two cycles of the P-bus cycle.
Transfer Request: The SIOF indicates a transfer request of the FIFO in the following two bits of
SISTR.
RXD_SIO
SIOFSYNC
TXD_SIO
SCK_SIO
1 by writing SITCR)
SIRCR) synchronously with the secondary FT.
CPU and DMAC. (One-stage 32-bit FIFO access cannot be divided into multiple accesses.)
FIFO
Setting: TRMD = 01,
Normal FS
Lch.DATA
No.0
Slot
TDLE = 1,
RDLE = 1,
CD0E = 1,
Figure 17.8 Control Data Interface (Secondary FS)
LSB = 1 (Secondary FS request)
1/2 frame
REDG = 0,
TDLA3 to TDLA0 = 0000,
RDLA3 to RDLA0 = 0000,
CD0A3 to CD0A0 = 0000,
1 frame
FL = 1110 (Frame length: 128 bits),
TDRE = 0,
RDRE =0,
CD1E = 0,
Secondary FS
channel 0
Control
No.0
Slot
Rev. 1.00 Dec. 27, 2005 Page 621 of 932
TDRA3 to TDRA0 = 0000,
RDRA3 to RDRA0 = 0000,
CD1A3 to CD1A0 = 0000
Section 17 Serial I/O with FIFO (SIOF)
1/2 frame
REJ09B0269-0100
Normal FS