HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 231

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

The area from H'F000 0000 to H'F0FF FFFF is for direct access to the cache address array. For
more information, see section 6.4, Memory-Mapped Cache.
The area from H'F100 0000 to H'F1FF FFFF is for direct access to the cache data array. For more
information, see section 6.4, Memory-Mapped Cache.
The area from H'F200 0000 to H'F2FF FFFF is for direct access to the TLB address array. For
more information, see section 5.6, Memory-Mapped TLB.
The area from H'F300 0000 to H'F3FF FFFF is for direct access to the TLB data array. For more
information, see section 5.6, Memory-Mapped TLB.
The area from H'FC00 0000 to H'FFFF FFFF is reserved for registers of the on-chip peripheral
modules. For more information, see section 23, List of Registers.
5. Uxy Area
The Uxy area is mapped to the on-chip memory of this LSI. This area is made usable in user
mode when the DSP bit in the SR register is set to 1. In user mode, accessing this area when
the DSP bit is 0 will result in an address error. This area cannot be accessed via the cache and
cannot be address-translated by the TLB. For more information on the Uxy area, see section 7,
X/Y Memory.
H'F000 0000
H'F100 0000
H'F200 0000
H'F300 0000
H'F400 0000
H'FC00 0000
H'FFFF FFFF
H'E000 0000
Figure 5.4 P4 Area
Control Register Area
Cache Address Array
TLB Address Array
Cache Data Array
TLB Data Array
Reserved Area
Reserved Area
Section 5 Memory Management Unit (MMU)
Rev. 1.00 Dec. 27, 2005 Page 187 of 932
REJ09B0269-0100