HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 72

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 2 CPU
2.1.2
This LSI supports two processing modes: user mode and privileged mode. These processing
modes can be determined by the processing mode bit (MD) of the status register (SR). If the MD
bit is cleared to 0, the user mode is selected. If the MD bit is set to 1, the privileged mode is
selected. The CPU enters the privileged mode by a transition to reset state or exception handling
state. In the privileged mode, any registers and resources in address spaces can be accessed.
Clearing the MD bit of the SR to 0 puts the CPU in the user mode. In the user mode, some of the
registers, including SR, and some of the address spaces cannot be accessed by the user program
and system control instructions cannot be executed. This function effectively protects the system
resources from the user program. To change the processing mode from user to privileged mode, a
transition to exception handling state is required*.
Note: * To call a service routine used in privileged mode from user mode, the LSI supports an
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REJ09B0269-0100
Processing Modes
unconditional trap instruction (TRAPA). When a transition from user mode to
privileged mode occurs, the contents of the SR and PC are saved. A program execution
in user mode can be resumed by restoring the contents of the SR and PC. To return
from an exception processing program, the LSI supports an RTE instruction.
(From any states)
Power-on reset
Manual reset
Exception handling state
exceptions
Multiple
Reset state
Figure 2.1 Processing State Transitions
routine starts
Exception
handling
Reset processing
routine starts
An exception
is accepted
An exception
is accepted
Program execution state
consumption state
Low-power
SLEEP instruction