HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 656

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 17 Serial I/O with FIFO (SIOF)
17.3.13 Serial Receive Control Data Register (SIRCR)
SIRCR is used to store the SIOF receive control data. SIRCR can be specified only when the FL3
to FL0 bits in SIMDR are specified as 1xxx. SIRCR is initialized by a power-on reset, software
reset, or receive reset.
Rev. 1.00 Dec. 27, 2005 Page 612 of 932
REJ09B0269-0100
Bit
31 to 16
15 to 0
Bit Name
SIRC015 to
SIRC00
SIRC115 to
SIRC10
Initial
Value
All 0
All 0
R/W
R
R
Description
Control Channel 0 Receive Data
Store data received from the RXD_SIO pin as control
channel 0 receive data. The position of the control
channel 0 data in the transmission or reception frame is
specified by the CD0A bit in SICDAR.
These bits are valid only when the CD0E bit in SICDAR
is set to 1.
Control Channel 1 Receive Data
Store data received from the RXD_SIO pin as control
channel 1 receive data. The position of the control
channel 1 data in the transmission or reception frame is
specified by the CD1A bit in SICDAR.
These bits are valid only when the CD1E bit in SICDAR
is set to 1.