HD6417712BPV Renesas Electronics America, HD6417712BPV Datasheet - Page 209

• Manufacturer Part Number: HD6417712BPV
• Description: MPU 1.5/3.3V 0K PB-FREE 256-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Ethernetr

Specifications of HD6417712BPV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, FIFO, SCI, SIO
• Peripherals: DMA, POR, WDT
• Number Of I /o: 24
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4.3
This section describes the conditions for specific exception handling, and the processor operations.
Resets and general exceptions are described in particular. For details on interrupt operations, refer
to section 8, Interrupt Controller (INTC).
4.3.1
Power-On Reset:
• Conditions
• Operations
Manual Reset:
• Conditions
• Operations
H-UDI Reset:
• Conditions
• Operations
Power-on reset is request
Set EXPEVT to H'000, initialize the CPU and on-chip peripheral modules, and branch to the
reset vector H′A0000000. For details, refer to the register descriptions in the relevant sections.
Be sure to perform power-On Reset at the time of a power supply injection.
Manual reset is request
Set EXPEVT to H'020, initialize the CPU and on-chip peripheral modules, and branch to the
reset vector H′A0000000. For details, refer to the register descriptions in the relevant sections.
An H-UDI reset command is input (see section 22.4.4 H-UDI Reset.)
EXPEVT is set to H'000, vector base register (VBR) and status register (SR) are initialized,
and branched to the reset vector (H'A0000000). VBR is cleared to H'00000000 by
initialization. In SR, the MD, RB, and BL bits are set to 1, the DSP bit is cleared to 0, and the
interrupt mask bits (I3 to I0) are set to B'1111. Then, the CPU and on-chip peripheral modules
are initialized. For details, see the Register Description in each section.
Individual Exception Operations
Resets
Rev. 1.00 Dec. 27, 2005 Page 165 of 932
Section 4 Exception Handling
REJ09B0269-0100