PNX1311EH/G,557 NXP Semiconductors, PNX1311EH/G,557 Datasheet - Page 146

• Manufacturer Part Number: PNX1311EH/G,557
• Description: IC MEDIA PROC 166MHZ 292-HBGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Ram Size: 48K x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 169
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 292-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Other names: 568-1295; 935277721557; PNX1311EH/G

PNX1300/01/02/11 Data Book
• LSB first, with 1–16-bit data per channel.
• Complex serial frames of up to 512 bits/frame.
• Up to 8 channels of audio output.
Table 9-1. AO unit external signals
9-2
AO_OSCLK
AO_SCK
AO_WS
Figure 9-1. AO clock system and I/O interface
Signal
AO_WS, left & right data in a frame).
AO_OSCLK
AO_SCK
AO_SDx
AO_WS
Type
OUT
(e.g. 256 f
(e.g. 64 f
IO
IO
Over sampling clock. Can be programmed
to emit any frequency up to 40 MHz, with
sub-Hz resolution. Intended for use as the
256 or 384f
external D/A conversion subsystem.
• When AO is programmed to act as a
• When AO is programmed to act as
AO_SCK is limited to 22 MHz. The sam-
ple rate of valid samples embedded within
the serial stream is limited by the
AO_SCK maximum frequency and the
available highway bandwidth.
• When AO is programmed as the serial-
• When AO is programmed as serial-
AO_WS is the word-select or frame-sync
signal from/to the external D/A sub-
system. Each audio channel receives 1
sample for every WS period.
AO_WS can be set to change on
AO_OSCLK positive or negative edges by
the CLOCK_EDGE bit.
s
s
)
)
serial interface timing slave (RESET
default), AO_SCK acts as input. It
receives the serial clock from the exter-
nal audio D/A subsystem. The clock is
treated as fully asynchronous to the
PNX1300 main clock.
serial interface timing master, AO_SCK
acts as output. It drives the serial clock
for the external audio D/A subsystem.
Clock frequency is a programmable
integral divide of the AO_OSCLK fre-
quency.
interface timing slave (RESET default),
AO_WS acts as an input. AO_WS is
sampled on the opposite AO_SCK
edge at which AO_SDx are asserted.
interface timing master, AO_WS acts
as an output. AO_WS is asserted on
the same AO_SCK edge as AO_SDx.
PRELIMINARY SPECIFICATION
s
Parallel to Serial Converter
oversampling clock by the
Description
div N+1
div N+1
SER_MASTER
8
7
16
16
32
WSDIV
SCKDIV
RIGHT[15:0]
LEFT[15:0]
AO_CC[31:0]
Table 9-1. AO unit external signals
9.3
The AO unit consists of three major subsystems, a pro-
grammable sample clock generator, a DMA engine and
a data serializer.
The DMA engine reads 16 or 32-bit samples from mem-
ory using a double buffered DMA approach. The
DSPCPU initially assigns two full sample buffers contain-
ing an integral number of samples for all active channels.
The DMA engine retrieves samples from the first buffer
until exhausted and continues from the second buffer,
while requesting a new first sample buffer from the
DSPCPU, etc.
The samples are given to the data serializer, which
sends them out in a MSB first or LSB first serial frame for-
mat that can also contain 1 or 2 codec control words of
up to 16 bits. The frame structure is highly programmable
by a series of MMIO fields.
9.4
Figure 9-1
AO unit. At the heart of the clock system is a square
wave DDS (Direct Digital Synthesizer). The DDS can be
AO_SD1
AO_SD2
AO_SD3
AO_SD4
9
Signal
DSPCPUCLK
0
0
SUMMARY OF OPERATION
INTERNAL CLOCK SOURCE
illustrates the different clock capabilities of the
Type
OUT
OUT
OUT
OUT
31
Serial data to stereo external audio D/A
subsystem. AO_SD1 can be set to
change on AO_OSCLK positive or nega-
tive edges by the CLOCK_EDGE bit.
Serial data to stereo external audio D/A
subsystem. AO_SD2 can be set to
change on AO_OSCLK positive or nega-
tive edges by the CLOCK_EDGE bit.
Serial data to stereo external audio D/A
subsystem. AO_SD3 can be set to
change on AO_OSCLK positive or nega-
tive edges by the CLOCK_EDGE bit.
Serial data to stereo external audio D/A
subsystem. AO_SD4 can be set to
change on AO_OSCLK positive or nega-
tive edges by the CLOCK_EDGE bit.
Square Wave DDS
Philips Semiconductors
FREQUENCY
Description
0