PNX1311EH/G,557 NXP Semiconductors, PNX1311EH/G,557 Datasheet - Page 368

• Manufacturer Part Number: PNX1311EH/G,557
• Description: IC MEDIA PROC 166MHZ 292-HBGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Ram Size: 48K x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 169
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 292-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Other names: 568-1295; 935277721557; PNX1311EH/G

Philips Semiconductors
Hardware 16-bit store with displacement
SYNTAX
FUNCTION
DESCRIPTION
the address in rsrc2 + d. The d value is an opcode modifier, must be in the range –128 and 126 inclusive, and must be
a multiple of 2. This store operation is performed as little-endian or big-endian depending on the current setting of the
bytesex bit in the PCSW.
h_st16d
the TRPMSE (TRaP on Misaligned Store Exception) bit in PCSW is 1, exception processing will be requested on the
next interruptible jump.
modification of the addressed memory locations (and the modification of cache if the locations are cacheable). If the
LSB of rguard is 1, the store takes effect. If the LSB of rguard is 0, h_st16d has no side effects whatever; in particular,
the LRU and other status bits in the data cache are not affected.
EXAMPLES
r10 = 0xcfe, r80 = 0x44332211
r50 = 0, r20 = 0xd05,
r70 = 0xaabbccdd
r60 = 1, r30 = 0xd06,
r70 = 0xaabbccdd
The
If
The
[ IF rguard ] h_st16d(d) rsrc1 rsrc2
if rguard then {
}
h_st16d
if PCSW.bytesex = LITTLE_ENDIAN then
else
mem[rsrc2 + d + (1
mem[rsrc2 + d + (0
h_st16d
h_st16d
bs
bs
is undefined, and the MSE (Misaligned Store Exception) bit in the PCSW register is set to 1. Additionally, if
Initial Values
1
0
is misaligned (the memory address computed by rsrc2 + d is not a multiple of 2), the result of
operation stores the least-significant 16-bit halfword of rsrc1 into the memory locations pointed to by
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
bs)]
bs)]
rsrc1<7:0>
rsrc1<15:8>
h_st16d(2) r80 r10
IF r50 h_st16d(–4) r70 r20
IF r60 h_st16d(–4) r70 r30
Operation
PRELIMINARY SPECIFICATION
PNX1300/01/02/11 DSPCPU Operations
[0xd00]
no change, since guard is false
[0xd02]
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
st16 st16d st8 st8d st32
st32d readpcsw ijmpf
0x22, [0xd01]
0xcc, [0xd03]
ATTRIBUTES
SEE ALSO
Result
h_st16d
0xdd
0x11
–128..126 by 2
dmem
7 bits
4, 5
n/a
30
2
A-70