PNX1311EH/G,557 NXP Semiconductors, PNX1311EH/G,557 Datasheet - Page 535

• Manufacturer Part Number: PNX1311EH/G,557
• Description: IC MEDIA PROC 166MHZ 292-HBGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Ram Size: 48K x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 169
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 292-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Other names: 568-1295; 935277721557; PNX1311EH/G

ISETTING2
ISETTING3
isub
isubi
izero
J
jmpf
jmpi
jmpt
JTAG
JTAG_CTRL
JTAG_DATA_IN
A B C
picture
picture
picture
additional registers
BYPASS instruction
communication protoco
example datat transfer
EXTEST instruction
instruction encodings
instructions
MACRO instruction
MMIO registers
overview
race condition,avoid
RESET instruction
SAMPLE/PRELOAD instruction
SEL_DATA_IN instruction
SEL_DATA_OUT instruction
SEL_IFULL_IN instruction
SEL_JTAG_CTRL instruction
SEL_OFULL_OUT instruction
system components
TAP controller description
TAP controller state diagram,picture
test access port
test clock 18-1,
test data in
test data out
test mode select
virtual registers
register
A-123
A-126
A-127
A-128
A-124
A-125
picture
table
SEL_DATA_IN
SEL_DATA_OUT
SEL_IFULL_IN
SEL_JTAG_CTRL
SEL_OFULL_OUT
table
3-10
3-10
3-10
18-4
D
18-1
18-2
18-4
18-1
18-4
18-1
E
18-3
18-4
18-1
18-1
18-2
F G
18-3
18-2
18-2
18-5
18-3
18-5
18-5
18-5
18-5
l18-5
18-5
18-5
18-1
18-2
18-3
H
18-3
18-3
18-3
18-2
I
18-2
J
K
L M N O P Q R S
JTAG_DATA_OUT
JTAG_IFULL_IN
JTAG_OFULL_OUT
K
keying
L
latency timer
latency,memory operation
ld32
ld32d
ld32r
ld32x
level sensitive interrupts
lines
load coefficients parameter table
load store ordering 3-3, 3-5, 3-7, 5-5, 17-4,
locking conditions
locking range
LRU bit definition
LRU bit definitions,picture
LRU bit update ordering
LRU initialization
LRU replacement,cache
LRU, hierarchical
LRU,four-way
LRU,two-way
lsl
lsli
lsr
lsri
M
macro block heade
macroblock header, standard references
main image
max_lat
Maximum Ratings
MEM_EVENTS
PRELIMINARY SPECIFICATION
A-133
A-135
A-134
A-136
register
register
chroma
color
PCI interface register
mirroring
PCI interface register
description table
picture
A-129
A-131
A-132
A-130
14-9
14-9
5-12
18-4
18-4
14-9
5-4
5-11
5-11
14-15
18-4
5-12
5-12
5-4
5-4
1-11
r15-1
18-4
5-13
5-12
3-10
5-11
5-12
5-8
11-7
11-9
T U V W X Y
14-22
15-3
17-6
Index-9
Z